The present invention relates to a semiconductor memory cell and a method of manufacturing the same.
Semiconductor memory elements, particularly, silicon dynamic memory elements have become highly integrated, and the memory cell area is decreasing. Since an amount of charge stored in one cell is limited by sensitivity of a sense amplifier and resistance to alpha-particles, the memory cell area cannot be reduced without limits. For this reason, various memory cell structures free from a decrease in charge amount even in an area smaller than that of a conventional cell have been proposed.
For example, there is a paper entitled as "Stacked Capacitor Cells for High-Density Dynamic RAMs", International Electron Devices Meeting Technical Digest, pp. 66-603, 1988.
In this paper, a memory cell having a structure shown in FIGS. 3A and 3B is proposed. This structure employs a layout called a "folded bit line structure" to assure noise resistance of a dynamic memory element. Each memory cell includes a first word line 302 for turning on/off the memory cell in an element region encircled by a boundary 301 and a second word line 303 for turning on/off a memory cell in an adjacent element region encircled by a boundary 301A in a direction parallel to a bit line 308. A capacitor of each memory cell is formed in a trench 304 as a stacked capacitor constituted of a charge storage polysilicon layer 305, a dielectric insulating film 309, and a counter electrode 313. This memory cell is characterized by a combination of a conventional stacked capacitor with a trench capacitor. When the memory cell area is to be reduced, this combination can easily assure a required storage capacitance as compared with a simple stacked or trench capacitor. The bit line 308 is formed on an insulating interlayer 307 and contacted with a source (drain) region 315 through a bit line contact hole 306 formed in the insulating interlayer 307 and an insulating interlayer 310. Reference numeral 316 denotes a gate insulating film.
In the conventional memory cell described above, as shown in FIG. 3B, since the trench capacitor is formed between the two word lines 302, 303 formed in the cell, an opening of the trench cannot be assured to be large, and a sufficient capacitance cannot be assured. This drawback is caused by the following reason. Since a fabrication process for simultaneously forming all word lines is employed, the second word line of a given cell is separated by a given gap from the second word line of a cell adjacent to the given cell in a direction parallel to the bit line. The distance between the two word lines within the given memory cell is shortened.